Bit line structure for semiconductor device

ABSTRACT

A bit line structure for semiconductor devices, and a fabrication method thereof are provided. In this method, a first conductive layer pattern, which fills a first contact hole and is used as a bit line, is formed on a first dielectric layer pattern having the first contact hole formed on a semiconductor substrate. A lower part protecting layer pattern, comprised of an anti-reflectance coating (ARC) layer used in a process for patterning the first dielectric layer pattern, is formed on the interface between the first conductive layer pattern and the first dielectric layer pattern. A spacer for covering the sidewall of the first conductive layer pattern is formed. An upper part protecting layer pattern comprised of an upper ARC layer is formed to cover the upper part of the first conductive layer pattern. A second dielectric layer pattern having a second contact hole is formed to cover the first conductive layer pattern. A second conductive layer pattern filling the second contact hole is formed and used as a storage node of a capacitor.

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This is a divisional of application Ser. No. 09/282,006, filedMar. 29, 1999, and which is incorporated by reference in its entirety.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to a semiconductor device, and moreparticularly, to a bit line structure in wiring structures and afabrication method thereof.

[0004] 2. Description of the Related Art

[0005] With an increase in the integration of semiconductor devices, acritical dimension decreases. Control of the uniformity of a criticaldimension becomes more and more important, thus increasing use of ananti-reflectance coating (ARC) film in a photolithographic process forpatterning a material film on a semiconductor substrate. The ARC filmhas been necessarily adopted in a process for patterning a conductivefilm which is used as a wiring structure such as a bit line, etc.

[0006] The ARC film is formed on a material film to be patterned andsuppresses diffused reflection on the surface of the material film.Since the diffused reflection on the surface of the material film issuppressed, accuracy by the photolithography can increase. Therefore, amore minute and uniform material film pattern can be attained.

[0007] The ARC film must be removed after the material film under theARC film is patterned, i.e., after a bit line is formed, since theremaining ARC film can serve as an etching stopper in a subsequentprocess and thus cause an etch failure or a contact hole formationfailure.

[0008]FIG. 1 is a cross-sectional view showing a conventional bit linestructure for a semiconductor device. Referring to FIG. 1, a bit line 60is formed on a first dielectric layer 23. Here, the bit line 60 iscomprised of conductive films, e.g., an impurity-doped polycrystallinesilicon layer 61 and a tungsten silicide layer 63.

[0009] A process for forming the bit line 60 is performed as follows.First, a direct contact hole and/or a direct contact pad can be formedby patterning the first dielectric layer 23 using a photolithographicprocess for interposing an ARC film on it. After removing the ARC film,a conductive film used as the bit line 60 is formed on the firstdielectric layer 23.

[0010] A second dielectric layer 25 covering the bit line 60 is formedafter the bit line 60 is formed. The second dielectric layer 25 ispatterned to form a buried contact hole 29 for exposing a semiconductorsubstrate 10. The buried contact hole 29 is cleaned, and anotherconductive layer for filling the contact hole 29, e.g., a storage nodeof a capacitor, is then formed. A conductive buried contact pad 31 canalso be formed below the buried contact hole 29.

[0011] Here, the bit line 60 may be damaged or oxidized by a subsequentprocess such as a storage node cleaning or forming process. Therefore, aspacer 27 for covering the sidewall of the buried contact hole 29 isintroduced to prevent damage to or oxidation of the bit line 60.

[0012] However, introduction of the spacer 27 on the sidewalls of theburied contact hole 29 substantially reduces the bottom criticaldimension of the buried contact hole 29, which may cause a reduction ina process margin in a subsequent process such as a process for forming aconductive film for filling the buried contact hole 29. Also, thecontact area, i.e., the interface, between the conductive film forfilling the buried contact hole 29 and the lower buried contact pad 31becomes substantially small, and thus a contact resistance can beincreased.

SUMMARY OF THE INVENTION

[0013] To solve the above problems, it is an object of the presentinvention to provide a bit line structure for semiconductor devices, bywhich a buried contact hole can be formed while oxidation of a bit lineis prevented, and an increase in contact resistance can be curbed sincea more bottom critical dimension of the buried contact hole can beattained.

[0014] It is another object of the present invention to provide a methodof fabricating a bit line structure for semiconductor devices, by whicha buried contact hole can be formed while oxidation of a bit line isprevented, and an increase in contact resistance can be curbed since amore bottom critical dimension of the buried contact hole can beattained.

[0015] Accordingly, to achieve the first object, there is provided a bitline structure for semiconductor devices, comprising: a first dielectricfilm pattern formed on a semiconductor substrate and having a firstcontact hole exposing a part of the semiconductor substrate; a firstconductive film pattern formed on the first dielectric film pattern,filling the first contact hole, and used as a bit line; a lowerprotecting layer pattern which protects the lower surface of the firstconductive layer pattern on the interface between the first conductivelayer pattern and the first dielectric layer pattern, and is comprisedof an anti-reflectance coating (ARC) layer; a spacer on the sidewall ofthe first conductive film pattern; an upper protecting layer patternwhich covers and protects the upper surface of the first conductivelayer pattern and is comprised of an ARC layer; and a second dielectriclayer pattern which insulates the first conductive film pattern, isisolated from the first conductive film pattern, and has a secondcontact hole for exposing the semiconductor substrate.

[0016] The spacer is formed of a nitride material selected from thegroup consisting of silicon nitride and silicon oxynitride. The lowerprotecting film pattern is a nitride-based ARC layer. The upperprotecting film pattern is a nitride-based ARC layer. A secondconductive film pattern for filling the second contact hole is furtherformed on the second dielectric film pattern.

[0017] To achieve the second object, there is provided a method offabricating a bit line structure for semiconductor devices. In thismethod, a first dielectric layer is formed on a semiconductor substrate.A lower ARC layer is formed on the first dielectric layer to preventdiffused reflection on the surface of the first dielectric layer. Afirst dielectric layer pattern having a first contact hole exposing thesemiconductor substrate is formed by patterning the lower ARC layer andthe first dielectric layer. A first conductive layer for filling thefirst contact hole is formed on the lower ARC layer. An upper ARC layerfor preventing diffused reflection on the surface of the firstconductive layer is formed on the first conductive layer.

[0018] A first conductive layer pattern used as a bit line is formed bysequentially patterning the upper ARC layer, the first conductive layer,and the lower ARC layer. Also, upper and lower protecting film patternsare formed, which are respectively comprised of the upper and lower ARClayers and protect the first conductive layer pattern. Here, the upperand lower protecting film patterns are nitride-based ARC layers.

[0019] A spacer is formed on the sidewall of the first conductive layerpattern. The spacer is formed of a nitride material selected from thegroup consisting of silicon nitride and silicon oxynitride. A seconddielectric layer pattern is formed, which covers the first conductivelayer pattern, is isolated from the first conductive layer pattern, andhas a second contact hole for exposing the semiconductor substrate.

[0020] After the step of forming the second dielectric layer pattern, asecond conductive layer pattern for filling the second contact hole isfurther formed on the second dielectric film pattern.

[0021] According to the present invention, oxidation of a bit line isprevented, and a second contact hole, e.g., a buried contact hole, canbe formed. Also, an additional spacer on the sidewalls of the buriedcontact hole can be excluded, thus a larger bottom critical dimensioncan be secured. Therefore, an increase in the contact resistance of asecond conductive film pattern filling the buried contact hole can beprevented. Furthermore, a spacer formation process can be omitted, tosimplify the bit line structure fabrication process.

BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The above objects and advantages of the present invention willbecome more apparent by describing in detail a preferred embodimentthereof with reference to the attached drawings in which:

[0023]FIG. 1 is a cross-sectional view illustrating a conventional bitline structure for semiconductor devices;

[0024]FIG. 2 is a lay-out illustrating a bit line structure according toan embodiment of the present invention;

[0025]FIG. 3 is a cross-sectional view taken along line A-A′ of FIG. 2,to explain a bit line structure according to an embodiment of thepresent invention;

[0026]FIGS. 4A and 4B are cross-sectional views, respectively, takenalong lines A-A′ and B-B′ of FIG. 2, illustrating the step of forming aconductive pad on a semiconductor substrate;

[0027]FIGS. 5A and 5B are cross-sectional views, respectively, takenalong lines A-A′ and B-B′ of FIG. 2, illustrating the step of forming afirst contact hole which is used as a direct contact hole for exposing adirect contact pad;

[0028]FIGS. 6A and 6B are cross-sectional views, respectively, takenalong lines A-A′ and B-B′ of FIG. 2, illustrating the step of forming afirst conductive film filling a first contact hole on a loweranti-reflectance coating layer;

[0029]FIGS. 7A and 7B are cross-sectional views, respectively, takenalong lines A-A′ and B-B′ of FIG. 2, illustrating the step of forming afirst conductive film pattern by patterning a first conductive film; and

[0030]FIGS. 8A and 8B are cross-sectional views, respectively, takenalong lines A-A′ and B-B′ of FIG. 2, illustrating the step of forming asecond dielectric film having a second contact hole which is used as aburied contact hole, on a first conductive film pattern.

DESCRIPTION OF THE PREFERRED EMBODIMENT

[0031] Hereinafter, embodiments of the present invention will bedescribed in detail with reference to the attached drawings. However,the embodiments of the present invention can be modified into variousother forms, and the scope of the present invention must not beinterpreted as being restricted to the embodiments. The embodiments areprovided to more completely explain the present invention to thoseskilled in the art. In the drawings, the thicknesses of layers orregions are exaggerated for clarity. Like reference numerals in thedrawings denote the same members. Also, when it is written that a layeris formed “on” another layer or a substrate, the layer can be formeddirectly on the other layer or the substrate, or other layers canintervene therebetween.

[0032] Referring to FIG. 2, a bit line structure according to anembodiment of the present invention includes a first conductive filmpattern 605 electrically connected to an active region 130 set on asemiconductor substrate 100. The first conductive film pattern 605 mustbe insulated from a gate electrode 170, and thus is electricallyconnected to the active region 130 via a contact hole and used as a bitline. For example, a first contact hole 400, e.g., a direct contacthole, is formed in a direct contact region, to thus electrically connectthe active region 130 to the first conductive film pattern 605.

[0033] Another conductive film can be formed on the first conductivefilm pattern 605. For example, a second conductive film pattern 700 ofFIG. 3 used as the storage node of a capacitor can be formed on thefirst conductive film pattern 605. Here, the storage node fills a secondcontact hole 300 formed in the buried contact region, e.g., a buriedcontact hole. That is, the bit line structure according to an embodimentof the present invention can be applied to a structure in which acapacitor has been formed on a bit line, i.e., a capacitor on bit line(COB) structure.

[0034] Referring to FIG. 3, a first dielectric film pattern 230 having afirst contact hole 400 of FIG. 2 is formed under the first conductivefilm pattern 605. Here, the first contact hole exposes part of asemiconductor substrate 100, e.g., the active region 130 of FIG. 2 of adirect contact region. A lower anti-reflectance coating (ARC) layer isintroduced on a first dielectric film in a process for forming the firstcontact holes 400 of the first dielectric film pattern 230.

[0035] The lower ARC layer prevents diffused reflection on the surfaceof a lower film, e.g., the first dielectric film, in a photolithographyprocess in which the first dielectric film pattern 230 is patterned,allowing formation of a minute pattern. Generally, the lower ARC layeris removed in a subsequent process. However, the embodiment of thepresent invention uses the lower ARC layer as a lower protecting filmpattern 515 for protecting the lower part or lower surface of the firstconductive film pattern 605.

[0036] That is, a first conductive film used as a bit line is formed onthe lower ARC layer without being removed. The lower ARC layer is alsopatterned when the first conductive film is patterned, thereby formingthe lower protecting film pattern 515 comprised of remaining parts ofthe lower ARC layer below the first conductive film pattern 605.

[0037] The lower ARC layer pattern 515 protects the first conductivefilm pattern 605 from a subsequent process. The protection of the firstconductive film pattern 605 from a subsequent process is completelyachieved by a spacer 570 for covering the sidewall of the firstconductive film pattern 605 and an upper protecting film pattern 555comprised of an upper ARC layer introduced when the first conductivefilm pattern 605 is patterned. At this time, the spacer 570, the upperprotecting film pattern 555, and the lower protecting film pattern 515are connected to one another, and thus better protection of the firstconductive film pattern 605 is achieved.

[0038] Oxidation of or damage to the first conductive film pattern 605in a subsequent high temperature process can be prevented by the lowerprotecting film pattern 515, the upper protecting film pattern 555, andthe spacer 570. For example, the first conductive film pattern 605 canbe prevented from being damaged or oxidized by a process for forming asecond contact hole 300 (see FIG. 2) such as a subsequent buried contacthole, a process for forming a second conductive film pattern 700 used asa storage node for filling the second contact hole 300, or a dielectricfilm forming process. To be more specific, the first conductive filmpattern 605 can be prevented from being oxidized or damaged by acleaning process introduced to form the second conductive film pattern700, a high temperature process, or an etch process for forming thesecond contact hole 300.

[0039] The upper and/or lower ARC layer can be formed of a materialwhich is usually used to form an ARC layer, e.g., a nitride-basedmaterial. To be more specific, a silicon oxy nitride (SiON) layer as thenitride-based material can be used. Accordingly, it is preferable thatthe spacer 515 is formed of silicon nitride (SiN), or SiON inconsideration of the interface or connection with or to the upper orlower protecting film pattern 555 or 515.

[0040] The protection of the first conductive film pattern 605 used asthe bit line from a subsequent process will be described in more detailwhile explaining a method of fabricating a bit line structure accordingto an embodiment of the present invention.

[0041] Referring to FIGS. 4A and 4B, an isolation film 150 for settingthe active region 130 of FIG. 2 is formed on a semiconductor substrate100. A third dielectric film 210 is formed using an interlayerdielectric (ILD) film covering the semiconductor substrate 100. Thethird dielectric film 210 is patterned to form a contact hole exposingthe active region, e.g., a buried contact hole 301 of FIG. 2 in a buriedcontact region, or a direct pad contact hole 401 of FIG. 2 in a directcontact region.

[0042] Conductive pads 310 and 410 for improving contact characteristicsare formed using the lower film of the first or second conductive filmpattern 605 of FIG. 2 or 700 of FIG. 3 respectively used as a bit lineor a storage node. For example, a buried contact pad 310 for filling theburied contact hole, or a direct contact pad 410 for filling the directcontact hole is formed.

[0043] Referring to FIGS. 5A and 5B, a first dielectric film 230 isformed of a dielectric material on the third dielectric film 210. Alower ARC layer 510 is formed on the first dielectric film 230. Thelower ARC layer 510 can prevent diffused reflection on the surface ofthe first dielectric film 230 in a photolithography process employed topattern the first dielectric film 230. Thus, a photoresist pattern offiner dimensions can be formed.

[0044] Any general ARC layer can be used as the lower ARC layer 510, buta nitride-based ARC layer is used in consideration of the subsequentstep of forming the spacer 570 of FIG. 3. For example, it is preferablethat an SiON layer, etc. is used.

[0045] The first dielectric film is patterned by the above-describedphotolithographic process for introducing the lower ARC layer 510, toform a first contact hole 400 corresponding to a direct contact hole forexposing the surface of the direct contact pad 410. The subsequent firstconductive film pattern 605 of FIG. 2 is electrically connected to theactive region 130 of FIG. 2 in the semiconductor substrate 100 via thefirst contact hole 400. Alternatively, the first contact hole 400 maydirectly expose part of the semiconductor substrate 100 withoutinclusion of the third insulative film 210 or the direct contact pad410.

[0046] Referring to FIGS. 6A and 6B, a first conductive film 600 isformed on the lower ARC layer 510. Here, the first conductive film 600fills the first contact hole 400 and is electrically connected to theactive region 130 (see FIG. 2) of the semiconductor substrate 100. Forexample, an impurity-doped polycrystalline silicon film 610 filling thefirst contact hole 400 is formed. Then, a tungsten silicide (WSi_(x))layer 630 is formed on the polycrystalline silicon layer 610. In thisway, a first conductive layer 600 to be used as a bit line is formed.

[0047] An upper ARC layer 550 is formed on the first conductive layer600. The upper ARC layer 550 prevents diffused reflection on the surfaceof the first conductive layer 600 in the photolithography process forpatterning the first conductive layer 600, thereby realizing the firstconductive layer pattern 605 (see FIG. 3) of fine dimension or highuniformity. Meanwhile, any ARC layer can be used as the upper ARC layer550, but a nitride-based ARC layer is used in consideration of the stepof forming the spacer 570 of FIG. 3. For example, it is preferable thatan SiON layer is used.

[0048] Referring to FIGS. 7A and 7B, a first conductive film pattern 605is formed by patterning the first conductive layer 600 using thephotolithographic process for including a photoresist pattern, etc. Atthis time, the upper or lower ARC layer 550 or 510 is also patterned,thereby forming a lower protecting layer pattern 515 which is placed onthe interface between the first conductive film pattern 605 and thefirst dielectric film pattern 230 and comprised of the remaining part ofthe lower ARC layer 510. An upper protecting film pattern 555 comprisedof the remaining part of the upper ARC layer 550 is also formed.

[0049] The spacer 570 is formed to cover the exposed sidewall of thefirst conductive film pattern 605. The spacer 570 is connected to theupper or lower protecting film pattern 555 or 515. Accordingly, thespacer 570 is formed of a material which is similar to the material ofthe upper or lower protecting film pattern 555 or 515, e.g., anitride-based material. For example, the spacer 570 is an SiN or SiONlayer.

[0050] As described above, the first conductive film pattern 605 isenclosed with the spacer 570, and the upper and lower protecting filmpatterns 555 and 515. Generation of damage to the first conductive layerpattern 605 can be better prevented. That is, when there is a hightemperature process in a subsequent process, such as formation of asecond conductive layer used as the storage node of a capacitor and/orformation of a dielectric layer of a capacitor, oxidation of or damageto the first conductive film pattern 605 is prevented by the spacer 570and the upper and lower protecting film patterns 555 and 515. Therefore,an increase in the resistance of the first conductive film pattern 605used as the bit line by oxidation, etc. is suppressed, and reliabilityof the bit line can thus be heightened. As a consequence, thereliability of semiconductor devices can be improved.

[0051] Meanwhile, the entire process can be simplified by introducingthe lower protecting film pattern 515 as described above. For example,the lower ARC layer 510 can generally serve as an etch stopper insubsequent processes. Accordingly, an additional etch process forremoving the lower ARC layer 510 must be performed after the process forpatterning the first dielectric film pattern 230.

[0052] However, in the embodiment of the present invention, the lowerARC layer 510, exclusive of a portion to be used as the lower protectingfilm pattern 515, is simultaneously removed in the patterning processfor forming the first conductive film pattern 605 used as the bit line.Thus, the additional etch process for removing the lower ARC layer 510can be omitted, so that the entire process becomes simpler.

[0053] Referring to FIGS. 8A and 8B, a second dielectric film coveringthe first conductive film pattern 605 is formed. The second dielectriclayer is patterned to form a second dielectric layer pattern 250 havinga second contact hole 300 exposing the lower buried contact pad 310 orthe semiconductor substrate 100.

[0054] A photolithographic process or an etch process for employing apolycrystalline silicon mask, etc. is used in the patterning process forforming the second dielectric layer pattern 250. Here, thepolycrystalline silicon mask can be used as an etch mask and/or as alower storage node stack in a subsequent process for forming acapacitor.

[0055] Then, the second conductive film pattern 700 of FIG. 3 fillingthe second contact hole 300 is formed. The second conductive filmpattern 700 can be used as the storage node of a capacitor in acapacitor on bit line (COB) structure. Accordingly, the secondconductive film pattern 700 of FIG. 3 can be formed of an impurity-dopedpolycrystalline silicon layer or an amorphous silicon layer. Thepolycrystalline silicon mask can also be adopted as a part of thestorage node.

[0056] Here, the embodiment of the present invention does not require aprocess for forming an additional spacer for covering the sidewall ofthe second contact hole 300. Generally, after the second contact hole300 is formed, an additional spacer is formed on the sidewall of thesecond contact hole 300 in a subsequent process, to prevent damage tothe first conductive film pattern 605. However, in the embodiment of thepresent invention, the first conductive film pattern 605 is covered withand protected by the lower protecting film pattern 515, the spacer 570for covering the sidewall of the first conductive film pattern 605, andthe upper protecting film pattern 555. Hence, there is no need to forman additional spacer on the sidewall of the second contact hole 300, andthus the bottom dimension of the second contact hole 300 can beincreased or ensured.

[0057] Also, deformation of the polycrystalline silicon mask can beprevented, which can occur in the process for forming an additionalspacer covering the sidewall of the second contact hole 300. To be morespecific, deformation of the polycrystalline silicon mask can be causedby a thermal process for forming a spacer on the sidewall of the secondcontact hole 300, e.g., by a high temperature process used to form anSiN layer. Accordingly, when the polycrystalline silicon mask is used asa part of a storage node in the subsequent process for forming acapacitor, there may be failure in a process for growing a hemisphericalgrained silicon layer. Thus, increasing the thickness of thepolycrystalline silicon mask becomes impossible.

[0058] However, in the embodiment of the present invention, a failure inprocesses such as growth of the hemispherical grained silicon layer canbe prevented by omitting the process for forming an additional spacercovering the sidewall of the second contact hole 300. Accordingly, thethickness of the polycrystalline silicon mask can be increased, and thusa small contact hole without a top critical dimension loss, i.e., thesecond contact hole 300, can be formed.

[0059] The present invention was described in detail referring to aspecific embodiment, but it is not limited to the embodiment. It isapparent that modifications or improvements may be effected within thetechnical spirit of the present invention by those skilled in the art.

What is claimed is:
 1. A bit line structure for semiconductor devices,comprising: a first dielectric layer pattern formed on a semiconductorsubstrate, the first dielectric layer pattern having a first contacthole exposing a part of the semiconductor substrate; a first conductivelayer pattern formed on the first dielectric layer pattern, filling thefirst contact hole, and used as a bit line; a lower protecting layerpattern which protects a lower surface of the first conductive layerpattern on an interface between the first conductive layer pattern andthe first dielectric layer pattern, the lower protecting layer patterncomprising an anti-reflectance coating (ARC) layer; a spacer on asidewall of the first conductive layer pattern; an upper protectinglayer pattern which covers and protects an upper surface of the firstconductive layer pattern, the upper protecting layer pattern comprisingan ARC layer; and a second dielectric layer pattern which insulates thefirst conductive layer pattern, is isolated from the first conductivelayer pattern, and has a second contact hole for exposing thesemiconductor substrate.
 2. The bit line structure for semiconductordevices as claimed in claim 1, wherein the spacer is formed of a nitridematerial selected from the group consisting of silicon nitride andsilicon oxynitride.
 3. The bit line structure for semiconductor devicesas claimed in claim 1, wherein the lower protecting layer pattern is anitride-based ARC layer.
 4. The bit line structure for semiconductordevices as claimed in claim 1, wherein the upper protecting layerpattern is a nitride-based ARC layer.
 5. The bit line structure forsemiconductor devices as claimed in claim 1, further comprising: asecond conductive layer pattern formed on the second dielectric layerpattern, for filling the second contact hole.
 6. The bit line structurefor semiconductor devices as claimed in claim 1, wherein the lowerprotecting layer pattern does not cover a sidewall of the first contacthole.